Dynamic FOC Wound Rotor Synchronous Starter-Generator

Published at 8/31/2026

#C
#STM32
#Motor Control
#FOC
#CAN Bus
#Web Serial
#Embedded
#Automotive
#Programming
#Personal

Overview

This project re-engineers an automotive hybrid Motor-Generator Unit (a 36V-rated MGU430-003 claw-pole motor with permanent magnet augmentation from a 2009 Saturn Vue Hybrid) to operate on a standard 12V vehicle bus.

Serving as the central powertrain controller, the system accomplishes three critical functions:

  1. Engine Belt-Start: Cranking an internal combustion engine up to starting speed through an accessory belt drive under full cylinder compression.
  2. Alternator Generation: Seamlessly transitioning into a closed-loop voltage-regulated alternator supplying vehicle electrical loads and battery charging.
  3. Active “Stall-Catch” Assist: Monitoring rapid engine RPM drops below idle and injecting instant torque assist to prevent engine stalls.


The Engineering Challenge: Why WRSM?

Unlike traditional permanent-magnet brushless motors (BLDC/PMSM) where rotor magnetic flux is fixed, a Wound Rotor Synchronous Motor (WRSM) allows active modulation of the magnetic field via rotor field current (If). This enables true dynamic field weakening without injecting reactive, heat-generating stator Id current.

However, standard Field-Oriented Control (FOC) algorithms in VESC assume fixed motor constants calculated once at boot. Because varying the field current dynamically alters stator inductance (Ld, Lq), magnetic saliency (Lq - Ld), and flux linkage (lambda), standard firmware would lose synchronization or destabilize.

Dynamic FOC Parameter Injection

To solve this, I bench-characterized the motor across field currents (0.0A to 3.0A), building multi-dimensional lookup tables that are injected directly into the real-time 20–30 kHz ADC DMA cycle (mcpwm_foc):

  • Live Flux Linkage: lambda(If) calculated and updated on the fly.
  • Live Saliency & Inductance Tracking: Dynamic updating of Ld(If), Lq(If), inverse saliency (1/Lq - 1/Ld), and High-Frequency Injection (HFI) parameters: 0.5 * (1/Ld + 1/Lq).
  • Preprocessor Compile-Time Safety: Implemented #define poisoning to eliminate accidental leakage of legacy static motor constants in the codebase.

Hierarchical Control Architecture

The firmware operates across four decoupled levels:

  1. Level 1 (Live Parameter Engine): Continuously reads field current ADC via DMA with moving-average filtering and updates the active FOC state structures.
  2. Level 2 (Field H-Bridge Driver): Timer-driven 5 kHz hardware PWM driving external BTS7960 H-bridges, featuring active field collapse for emergency shutdown.
  3. Level 3 (Field Current PID): Closed-loop regulator dynamically calculating target field current based on instantaneous stator torque demand (Iq).
  4. Level 4 (Master Powertrain Supervisor):
    • Start Mode: Executes a speed PID ramp up to 200+ engine RPM with a speed ratchet to capture engine firing acceleration, I-term wind-down, and smooth open-loop current to sensorless observer handoff without stall dropouts.
    • Alternator Mode: Regulates vehicle bus voltage (V_batt) via closed-loop PID commanding generating current.
    • Stall-Catch Mode: Monitors deceleration rates below 1,000 RPM, instantaneously triggering torque assist at 500–600 RPM to catch an impending engine stall before safely handing back to alternator mode.

The Ecosystem of Sub-Projects Spawned

Executing this powertrain controller required solving several system-level challenges, comprising the core firmware fork and three dedicated open-source sub-projects:

1. bldc (feature/wrsm) — Custom VESC Firmware Fork

The core motor controller firmware powering the system, refactored from Vedder’s open-source VESC codebase for bare-metal STM32F405 hardware:

  • Dynamic Parameter Injection: Injects live multi-dimensional lookups for flux linkage and saliency into the real-time FOC DMA cycle.
  • Closed-Loop Field Regulation: Hardware timer-driven 5 kHz PWM driving external BTS7960 H-bridges with PID field current control and fast collapse.
  • Supervisory Powertrain Logic: Multi-tier state machine executing compression start ramps, alternator voltage regulation, and active anti-stall assist.

2. vesc_web_tool — Web Serial Diagnostic Suite

Rather than relying on heavy native desktop toolchains for bench testing, I built a zero-dependency browser interface utilizing the modern Web Serial API:

  • Connects directly from Chrome/Edge to the microcontroller over physical USB serial.
  • Live binary packet decoding, real-time telemetry plotting, start diagnosis capture, and interactive terminal commands.

3. VRR-to-EABI — Real-Time Resolver Demodulator Firmware

Zero-speed engine starting under compression requires high-precision rotor angle feedback where sensorless observers struggle. I developed bare-metal firmware on an STM32F407 (168 MHz ARM Cortex-M4F) to convert Variable Reluctance (VR) resolver signals into zero-latency hardware quadrature pulses (ABI):

  • Zero-Overhead Carrier: 15 kHz sinusoidal excitation generated via 12-bit DAC + circular DMA triggered by TIM6 at 480 kHz.
  • Synchronous Peak Sampling: Dual simultaneous ADC conversions at 30 kHz timed to exact carrier peaks, eliminating DC bias and ground-loop noise.
  • Predictive PLL Tracking: 40 µs velocity feedforward prediction eliminating phase lag up to 20,000 RPM.

4. core-can-bus-spec — Motorsport CAN Architecture & DBC

To coordinate the starter-generator with the vehicle’s engine management system (rusEFI ECU), digital dashboard, and auxiliary electric pumps/fans, I authored a system-wide 500 kbps CAN 2.0A DBC specification:

  • Motorsport Tiered Partitioning: Standardized address space mirroring MoTeC/Bosch standards (Emergency E-stop, Driver Controls, Dual-setpoint CC/CV commands, Powertrain Telemetry, Diagnostics).
  • Dual-Setpoint Commands: Frame structures passing simultaneous target speed (CV) and dynamic maximum current clamps (CC) for thermal and hydraulic protection.

Judson Hartley © 2023-2026